16-Bit ADC ASIC with Analog Front End
Unveil the pinnacle of precision with our advanced 16-Bit ADC ASIC featuring an Analog Frontend. This meticulously engineered solution redefines signal acquisition and processing, boasting a 16-bit ADC core for unmatched resolution. Designed with a high-performance Sample-and-Hold circuit, Programmable Gain Amplifier (PGA), and Offset Cancellation DAC, this ASIC ensures adaptability and error mitigation. With features like a 0.1 to 20 MSPS sampling rate, absence of missing codes, and low power consumption (86mW), it stands as a testament to innovation and precision in data conversion for a multitude of applications.
→ 16-Bit ADC Core
→ High Performance Sample-and-Hold Circuit
→ Programmable Gain Amplifier (PGA)
→ Offset Cancellation DAC
→ Correlated Double Sampler (CDS)
→ Clamp Circuit for interfacing to CCD sensors
→ Internal Voltage Reference
→ Clock Management Unit
→ SPI IF
→ Sampling Rate: 0.1 to 20 MSPS
→ No Missing Codes
→ Monotonicity
→ INL: ±2LSB
→ Power Consumption: 86mW
→ Temperature Drift: 35 ppm/degC
→ CDS Timing: 4 to 46 ns at 20 MHz Input Clock